As with the process technologies used to make logic chips, DRAM ICs require the use of EUV lithography as transistors become smaller. Today, Samsung and SK hynix use EUV for a few layers, which is expensive. To make EUV significantly cheaper, DRAM makers will need to use three-dimensional transistors and new DRAM structures, a researcher from SK hynix said at an industry conference, The Elec reports.
DRAM manufacturers are constantly striving to make their memory cells and their ICs as small as possible to be more competitive. They typically do this by using new process technologies and new DRAM cell structures every decade or so. For example, today’s DRAMs use a 6F^2 (6F2) cell design, which has used three-dimensional FinFET transistors for over a decade. DRAM uses simple transistors primarily because each new process node introduced new ways to shrink DRAM cells, which was all the memory manufacturers needed.
But preserving 6F^2 cells and simple transistors with EUV does not seem as promising as once thought, according to SK Hynix researcher Seo Jae Wook, speaking at an industry event. He says that with vertical channel transistors (VCTs) or 3D DRAM, “the process can be designed to reduce the cost of EUV processes by half.”
Meanwhile, The Elec reports that SK hynix is preparing to combine VCT and 4F^2 (4F2) cell design to produce ultra-dense DRAMs (arguably a risky but ambitious move). However, the memory maker has not publicly confirmed such plans. So, when SK hynix starts using EUV more extensively a few years down the line, the company will have experience with both VCTs (e.g. FinFET or even gate-all-around transistors) and 4F^2 cell structures. The latter promises a 30% reduction in DRAM density compared to 6F^2 at the same node.
Fab tool maker Tokyo Electron expects DRAMs with Vertical Channel Transistors (VCTs) and a 4F^2 cell design to hit the market around 2027 to 2028. The company also expects memory manufacturers to need to use new materials for capacitors and bit lines to produce these VCT-based DRAMs.
SK hynix and Samsung reportedly plan to adopt a 4F^2 cell design with their sub-10nm process technologies, but details are scarce. Samsung’s first-generation sub-10nm DRAM manufacturing process is still two generations away. Currently, Samsung’s most advanced DRAM production node is the 5th generation 10nm-class (12nm) technology, which the company has been using since mid-2023. According to a slide leaked earlier this year, Samsung plans to develop two more 10nm-class manufacturing processes before unveiling the first-generation sub-10nm node, which is expected to launch in the second half of the decade.
In addition to using EUV, 4F^2 cell design and VCT transistors, Samsung plans to implement stacked DRAM process technology in the early 2030s, which will further increase the density of its memory devices in the next decade.
